1. Field of the Invention
The present invention relates in general to a fabrication method for a semiconductor device. More particularly, it relates to forming gate spacers in an array area and a peripheral area.
2. Brief Discussion of the Related Art
MOSFETs have been continuously scaled down to gain improved device density, operating performance, and reduced fabrication cost for integrated circuits (ICs). With MOSFET channel length decreased, the gate of the MOSFET is barely able to switch off the conductive channel thereunder. This phenomenon is known as the short channel effect, which is especially significant when a MOSFET has a channel length less than 0.13 um.
In a dynamic random access memory (DRAM), for example, shrinkage of memory cells in array areas yields higher device density, better production efficiency, and lower product cost. This shrinkage, however, also enlarges the short channel effect on the transistors in peripheral areas, easily causing peripheral circuit to malfunction.
Therefore, novel technologies are needed for accommodating cells both in array and periphery areas to downsized memories.